Overlay RAM

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Symoon
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Overlay RAM

Post by Symoon »

Hi,

Sorry, I guess this question has been asked before but I didn't find where.
So: how complicated would it be to design something so that simple Orics without disk drive can access to the overlay RAM?
A simple switch plugged to the ROMDIS and somewhere else (?) or something like this would be enough?
All software problems put aside...

I'd like to POKE in this area, one day, without disk drive ;-)
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Dbug
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Post by Dbug »

There was an expansion board doing that, schematics were published in some issue of Theoric.

Now possibly with modern components it could perhaps be done with a more limited amount of stuff to solder :)

Now, conceptually, I believe it could be possible to do something that is not compatible with the way the microdisc is working. After all if there is no way to control a disk, no need to be compatible. Perhaps we could just use the free register (pb 6?) connected to one of the existing oric chip (don't remember if it's the YM or the VIA), and use that to set the value of ROMDIS.

Would be probably a couple of resistors/transistors :)

Hardware experts, doable ?
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Post by JamesD »

Dbug wrote:There was an expansion board doing that, schematics were published in some issue of Theoric.

Now possibly with modern components it could perhaps be done with a more limited amount of stuff to solder :)
I'm sure that could fit in one chip now and a pretty small one at that. Decoding the address requires a lot of pins though.
Now, conceptually, I believe it could be possible to do something that is not compatible with the way the microdisc is working. After all if there is no way to control a disk, no need to be compatible. Perhaps we could just use the free register (pb 6?) connected to one of the existing oric chip (don't remember if it's the YM or the VIA), and use that to set the value of ROMDIS.

Would be probably a couple of resistors/transistors :)

Hardware experts, doable ?
No need to be compatible... the exact thing I get ripped on for suggesting with a mass storage device.

First of all, I don't think it's just ROMDIS. I think there was one other signal to control the RAM. That way a plugin device could have it's own ROM.

The YM port 14 is used for the keyboard and the port 15 has no outputs on the chip in the Oric.

As for the VIA, I don't think it's an unused port but an unused pin.
Port B pin 5 does not appear to be connected on the diagram I'm looking at. If it were used as an output the value on other pins could be latched for controlling the two (from memory) signals dealing with the ROM/RAM overlay area. As long as you are aware this could mess up reading the keyboard and that is left in an interrupt there should be no problem.
Just switching existing memory would be pretty simple.

Now, you could latch PB0-PB3 as a page select. If you don't mind reusing the YM port 14 you could latch it as well. This be used as a simple memory paging system with 12 bits to select 16K pages. 1 page would be the ROM, 1 the current overlay RAM, and the rest new RAM. That's 4096K + 48K for 4144k total memory if you include the ROM.
But since that sounds like overkill you could just use the lower pins on Port B and add a 256K RAM - the ROM and current RAM.
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Symoon
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Post by Symoon »

Mmmmh, so it seems much more complicated than what I thought ;-)
I just imagined a small switch plugged somewhere could have been enough.
That was too easy :?
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Post by JamesD »

If just switching ROM and RAM then the circuit would be something like this:

PB5 = ENABLE
PB4 = RAMROM

If ENABLE is 1, latch PB4

the output from that latch has a pass through to /ROMDIS
It also has an inverted output that is passed to /MAP

RESET should restore the latch to 0

That's three inputs and 2 outputs.

<edit>
There is one small catch. If the keyboard output on PB4 is high, that could trigger the overlay RAM when you are trying to trigger ROM.
You have to write $00 to the AY port 14 to make sure it's clear first.
Otherwise you have to hack PB4 so the keyboard output is blocked when PB5 (ENABLE) is active. If you don't mind cutting a trace it would just be one more input to a PAL/GAL and the line to PB4 would be I/O not just input.

You might also be able to latch PB0-PB3 at the same time and just pass then through for future memory paging.
That's 4 inputs and 6 outputs. With power and ground the chip must have at least 12 pins.
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Post by JamesD »

Hmmm... with the memory paging /MAP would also be impacted.
I'd need to think on it a while but it's logic is something like this:

If (ROMRAM = 1) and (PB0 = 0) and (PB1 = 0) and (PB2 = 0) and (PB3 = 0) then /MAP = 1

or something like:
/MAP = NOT(ROMRAM AND (NOT PB0) AND (NOT PB1) AND (NOT PB2) AND (NOT PB3))
/ROMDIS = ROMRAM
MEM0 = PB0
MEM1 = PB1
MEM2 = PB2
MEM3 = PB3


I haven't been doing hardware lately so I'd have to look up the proper way to write it. Keep in mind that PB signals are the latched versions and those are latched when ENABLE is active.
<edit>
I just found where we were talking about this before.
When /MAP AND /ROMDIS are active, that 16K is mapped to an external device.

When /MAP is inactive and /ROMDIS is inactive, that 16K goes to the standard ROM.

When /MAP is inactive and /ROMDIS is active, that 16K goes to the overlay RAM.
So I have the logic wrong.
RESET would also have to set the memory paging lines to 0
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Post by JamesD »

Without paging lines:

/ROMDIS = /PB4
/MAP = 1

That's pretty simple.

With paging:

/ROMDIS = NOT PB4
/MAP = NOT(PB4 AND(PB3 OR PB2 OR PB1 OR PB0))

At least I think that's it.
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Post by JamesD »

One oversight... expansion RAM needs a select line to see when it's active.
Additional logic for addressing the expansion RAM would need to be external.
<edit>
If the expansion RAM select needs to be active low then /MAP could be used for it as well. If it needs to be active high, then it would be the equation before it was inverted to send to /MAP. At most an additional output but not much of a change.
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Post by JamesD »

For expansion RAM it would be something like this:

Oric.........Expansion RAM
A0-A13....A0-A13

PB0-PB3...A14-A17


New chip select AND A15 AND A16 -> RAM CS
With only a couple more inputs the chip select for the expansion RAM would be done and you just need A0-A13 from the Oric bus. The rest would be from this chip.


PB0-PB5 Input (PB4 I/O if you don't want to clear AY) - 6 pins
Normal PB4 Input (optional?) - 1 pin
Oric A15-A16 Input - 2 pins
Buffered PB0-PB3 Output as A14-A18 for expansion RAM - 4 pins
/ROMDIS Output - 1 pin
/MAP as Output - 1 pin
Expansion RAM select as Output - 1 pin

That would require 17 pins for the full thing, 16 if you clear AY port 14 before paging. PB4 may need a diode protecting the existing circuit so it might be better to switch that line if there isn't already a diode on it.
Last edited by JamesD on Sun Jul 19, 2009 11:50 pm, edited 1 time in total.
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Post by JamesD »

DISCLAIMER!
I make no claims as to the accuracy of the following circuit.
Any mods to your Oric is at your own risk so don't yell at me if it doesn't work or kills your machine.

This *should* work as the simple circuit.

http://pdf1.alldatasheet.com/datasheet- ... LS373.html
http://pdf1.alldatasheet.com/datasheet- ... 4LS04.html

74LS373
tie /OC low (Pin 1)
PB5 to diode to C (Pin 11)
PB4 to D (Pin 3)
Pin 2 to LS04 Pin 13

74LS04
input from LS373 pin 2 goes to pin 13
pin 12 goes to /ROMDIS
/Reset goes to pin 11
pin 10 goes to diode to LS373 pin 11

The diodes isolate PB5 and the LS04 from each other.
That's for the reset.
I'm guessing the Reset will trip the VIA lines back to 0. If not it's going to take more logic.

Connect power and ground to appropriate pins.
This shouldn't generate a lot of noise so I don't think you'll need a decoupling cap.
<edit> Check last revision date to make sure I didn't change anything.
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Post by JamesD »

PB0 is pin 10 of the 6522
.
.
.
PB4 is pin 14
PB5 is pin 15
Reset (/Rst) is pin 34 or pin 4 of the expansion connector

/MAP is pin 26 of the ULA or pin 1 of the expansion connector
/ROMDIS is pin 27 of IC9 (ROM) or pin 2 of the expansion connector

The diagram shows pin 27 of IC10 (ROM) isn't connected to /ROMDIS, is this is in error? (2nd link)

http://oric.ifrance.com/oric/images/oric1-1s.gif
http://oric.ifrance.com/oric/images/oric1-2s.gif


This could tie in with a ROM replacement. Perhaps it might be better to use the new address lines to expand the ROM. If the internal ROM is replaced with a 256K FLASH this would let the entire chip be used. It also means we don't have to control /MAP and the interface can work with an external expansion without difficulty.

To latch the new lines from PB0 - PB3, just attach then to the 74LS373's unused data input lines and the outputs to the high address lines on the ROM/FLASH/Whatever. If we use PB7 (goes to TAPE OUT, I don't think we will be writing to tape and paging memory at the same time) then it could address 512K. PB6 appears to control a tape on/off relay(?) so we can't use it. If you do want to have cassette I/O while paging memory you need to maintain the setting for PB6.
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Post by JamesD »

JamesD wrote: When /MAP AND /ROMDIS are active, that 16K is mapped to an external device.

When /MAP is inactive and /ROMDIS is inactive, that 16K goes to the standard ROM.

When /MAP is inactive and /ROMDIS is active, that 16K goes to the overlay RAM.
One little problem. I'm looking at the schematic and /ROMDIS doesn't connect to the ULA. Something has to tell the CPU to enable RAM in that space. Since /MAP is held high normally it must be pulled low to enable the overlay RAM. So the signal out of the LS373 pin 2 must also go to /MAP... but probably by going through another gate first (2 more inverters?)
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Post by JamesD »

Before anyone goes out and tries to build this, I have a question.
Is this how you really want to use the only unused pin on the VIA chip?

There are many other things this could be used for and I think I already had something else in mind at one point in time.

After reading an older thread where we talked about this, I ran across a comment I made about adding a DAC to the sound output.
The same latch mentioned in this thread could be triggered by the same pin (PB5) to capture the AY port 14 output and it's output could be routed through a DAC (different resistors on each pin will work), then through a diode and to the input to the amplifier on the Oric's motherboard. This would allow easier playback of sound samples than with the standard AY ports.

Not only that but PB4 could be used to select between two different latches. One for the sound output and the other to select the ROM/FLASH/whatever memory page. Just add an chip with at least 2 dual input AND gates (NAND?) and pass PB4 through an inverter before the AND for the 2nd port.

Since this would be new hardware I seen no compatibility issues for the last 2 purposes. But for the memory overlay it might be best to stick to the standard.
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Post by highwayman »

it may be possible without any extra chips,
but you need to know the state of the via outputs at reset,

also, you must write a trap handler into $FFFA-FFFF for safety before you disable the rom or an irq/nmi could crash the system.
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Post by JamesD »

highwayman wrote:it may be possible without any extra chips,
but you need to know the state of the via outputs at reset,

also, you must write a trap handler into $FFFA-FFFF for safety before you disable the rom or an irq/nmi could crash the system.
/ROMDIS and /MAP are active low. At the very least I think it would need an inverter or have to modify the ROM.

If you switch out the ROM I think it's a given you need to disable interrupts until the RAM overlay is properly set up.

<edit> Any code that accesses port B must be sure to leave the pin as an output and it will need to OR the current PB5 setting with any write to the port.
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